Simulation-Based Power Estimation of Low Power MD5 Design Techniques

Shamsiah Binti Suhaili1, and Takahiro Watanabe2

1. Faculty of Engineering, Universiti Malaysia Sarawak, 94300 Kota Samarahan, Sarawak, Malaysia

2. Graduate School of Information, Production and Systems, Waseda University, Japan

Abstract: Hash function is important in security system design where transmission of data need to be secured enough to avoid eavesdropping and unauthorized monitoring. Efficient implementation needs to be considered in designing MD5 hash function in terms of high speed, small area and low power design. The objective of this project is to obtain low power MD5 design as well as balancing between maximum frequency and area implementation. Therefore, two low power design techniques have been proposed in order to reduce the power consumption of MD5 hash function such as state encoding and clock gating. In this paper, four different types of MD5 were successfully designed based on Arria II GX Altera Quartus II namely MD5_Binary, MD5_Gray, MD5_Gating and MD5_Gray_Gating. These designs were simulated using ModelSim to evaluate the correctness of the output results. Dynamic power is consumed when signal change their logic state in CMOS transistor. In this paper, dynamic power dissipation of MD5 Gray encoding with clock gating reduce significantly which is 20.72% if compared with MD5 Binary encoding. Furthermore, MD5 Binary encoding with clock gating provides efficient implementation in terms of speed, area and power. From this analysis, simulation-based power estimation generated from the PowerPlay Power Analyzer Altera Quartus II can provide accurate power estimation.

Key words: MD5, simulation-based power, PowerPlay